(a) Field of the Invention
The present invention relates to a process for forming isolation regions for electrically isolating devices constituting semiconductor integrated circuits, and more particularly to a process for forming trench isolation regions by forming device isolation trenches in a semiconductor substrate and refilling the trenches with an insulation film.
(b) Description of the Prior Art
The packing density, for example, of DRAMs (dynamic random access memories) has increased approximately at a rate of fourfold every three years, and with this trend, the minimum line width of circuits has decreased by about 60% to 70% from generation to generation. Consequently, 1 Mb DRAM and 4 Mb DRAM presently made available by mass production are 1.2 .mu.m and 0.8 .mu.m, respectively, in minimum line width. Further 16 Mb DRAMs which have yet to be produced in quantities are 0.6 to 0.5 .mu.m in minimum line width. 64 Mb DRAMs to be developed in the future will be 0.4 to 0.3 .mu.m in minimum line width.
With semiconductor devices thus made more microscopic, the isolation regions for isolating the devices from one another have become gradually narrower. In minimum isolation width, 4 Mb DRAMs are 1.0 to 0.8 .mu.m, 16 Mb DRAMs are 0.8 to 0.6 .mu.m, and 64 Mb DRAMs will be reduced to 0.5 to 0.4 .mu.m.
The device isolation regions having a width of at least 0.6 .mu.m can be formed by local oxidation of silicon isolation (LOCOS process) or improved LOCOS process. The LOCOS process is such that a silicon nitride film covering a silicon substrate is apertured by patterning, and the exposed silicon substrate surface is selectively oxidized to form a silicon oxide film serving as an insulation film.
For the following reason, however, the LOCOS process is unable to form isolation regions of up to 0.5 .mu.m. Unless the oxide film on the isolation regions is made extremely thin, the LOCOS process permits oxidation of the silicon substrate to progress to regions covered with the silicon nitride film to result in side-wise extensions of silicon oxide film called bird's beaks. Thus, the isolation regions spread out beyond the mask size, making it impossible to form narrow isolation regions.
As an alternative to the LOCOS process, the so-called trench isolation process has been proposed. With this process, a resist pattern formed by lithography is used as an etching mask to form recessed trenches in a silicon substrate, and the trenches are filled up with an insulator such as a silicon oxide film.
FIGS. 4(a) to (e) are diagrams showing the conventional trench isolation process, which will be described with reference to FIG. 4(a) to (e).
(1) First, a thin oxide film 44 is formed over the surface of a silicon substrate 41, a polycrystalline silicon film 45 is thereafter deposited on the film, and the portions 42, 43 to be made into isolation regions are etched by reactive ion etching to form a trench 42 of small width and a trench 43 of large width (FIG. 4, (a)).
(2) Next, the inside of the trenches 42, 43 is cleaned, the surface is oxidized to form a thin oxide film 46 and subsequently coated with a thin silicon nitride film 47, and a silicon oxide film 48 of a thickness approximately corresponding to the depth of the trenches is deposited on the nitride film to fill up the trenches. This step produces a higher step 49 around the wide isolation region 43 (FIG. 4, (b)).
(3) A dummy resist layer 50 is then formed on the wide isolation region 43 so that the silicon oxide film 48 will not be removed from this region 43 when the silicon oxide film 48 is removed from the active regions for forming transistors. After the dummy resist layer 50 has been formed, polyimide resin 51 is coated on the surface to fill up the space between the dummy resist layer 50 and the step 49 to form a planar surface (FIG. 4, (c)).
(4) Next, to remove the polyimide resin 51 and the oxide film 48 on the active regions, the entire surface is etched by reactive etching at equal rates for the polyimide resin, the resist resin material and the oxide film. The etching is stopped upon the polycrystalline silicon film 45 appearing on the surface (FIG. 4, (d)).
(5) The polycrystalline silicon film 45 is etched away, the surface is cleaned and the oxide film 44 is further removed with hydrofluoric acid, followed by a transistor forming process (FIG. 4, (e)).
Thus, the use of the trench isolation process forms trench regions which only serve as the isolation regions, so that the isolation width can be reduced to a value limited by lithograph. The trench isolation process is therefore suitable for isolating the devices of semiconductor integrated circuits of increased packing densities.
In the conventional trench isolation process described above, however, the oxide film 48 deposited in the step (2) is as thick as about 1 .mu.m. In order to fill the trenches completely, there is a need to resort to the LP CVD (Low Pressure Vapor Deposition) process with good step-coverage. This method nevertheless has the drawbacks of being low in film deposition rate and poor in throughput.
Further, in the case that the total thickness of the resin film and the oxide film is about 2 microns, the oxide film will be overetched by 800 angstroms at portions where the etching proceeds at the highest rate, even if the in-plane uniformity of the equal-rate etching condition for the resin film and the oxide film is within .+-.2% Accordingly, unless the rate of etching of the polycrystalline silicon film 45 is very small under the equal-rate etching condition, the active regions also are etched and thereby damaged. Even if the etching is stopped at the polycrystalline silicon film 45 as desired, a distinct step with a height of about 800 angstroms will occur between the isolation region and the active region.
When the surface of the oxide film within the trench is lower than the silicon surface in the active region, an electric field will be concentrated at the edge of the active region since the wiring for the gate electrode is so provided as to cover the corner portion of the active region. This field concentration gives rise to the problem that a leak current occurs in the subthreshold region of the transistor.
Further as shown in FIG. 4, (e), the treatment with hydrofluoric acid creates a wedgelike minute ditch 52 in the center of the trench 42 with a large aspect ratio. Usually the formation of the isolation regions is followed by the formation of the gate insulation film and gate electrode wiring for MOS transistors. The presence of the minute ditch 52 in the isolation region entails the problem of a break in the wiring, or a short circuit between the wirings, which would occur if the wiring material remains in the minute ditch.
The known references on a semiconductor device isolation technology are as follows.
1. "A NEW TRENCH ISOLATION TECHNOLOGY AS A REPLACEMENT 0F LOCOS" PA0 2. "A PRACTICAL TRENCH ISOLATION TECHNOLOGY WITH A NOVEL PLANARIZATION PROCESS" PA0 3. "BURIED-OXIDE ISOLATION WITH ETCH-STOP (BOXES)" PA0 4. IBM Technical Disclosure Bulletin Vol. 23, No. 11 PA0 5. IBM Technical Disclosure Bulletin Vol 24, No. 7B
H. Mikoshiba, T. Homma and K. Hamano PA1 G. Fuse et al. PA1 IEDM Technical Digest, 1987 P732.about.735 PA1 Robert F. Kwasnick et al. PA1 IEEE ELECTRON DEVICE LETTERS. Vol. 9, No. 2 PA1 Feb. 1988 PA1 Apr. 1981 PA1 Dec. 1981
IEDM Technical Digest, 1984 P578.about.581